(1) Field of the Invention
The present invention relates to a semiconductor memory device realizing high-speed access by division of a bit line.
(2) Description of the Related Art
By advancement of process generation, recently, there is increased a demand for high-speed data read from a memory. In conventional data read using a sense amplifier, it takes much time to draw an electrical charge from a bit line by a memory cell due to variations in transistor characteristics based on process subdivision, in particular, variations in current performance of the memory cell. Consequently, a time for access tends to be long.
In order to realize high-speed access in such a manner that a bit-line capacitance is decreased by division of a memory cell array, heretofore, various techniques are proposed. In a technique that data is read while being amplified by a hierarchical sense amplifier by division of a memory cell array, for example, an increase in circuit scale at a hierarchical part exerts a considerable influence on an area of a macro in a semiconductor chip.
In addition, there is proposed a technique that data is read by using a global read signal line at a hierarchical part (refer to, for example, JP2005-025859A and Japanese Patent No. 2744144).
Further, there is proposed a technique that data on a plurality of bit lines are outputted while being transferred to a single global bit line in advance (refer to, for example, Japanese Patent No. 3452497).
In a conventional semiconductor memory device, since a global bit line is provided for each bit line, a frequency of interconnections increases as bit lines increase in number. This hinders suppression of an increase in area in a case that a memory is mounted on a system LSI together with another component.
On the other hand, if data on a plurality of bit lines are outputted while being transferred to a single global bit line in advance by means of a switch in order to reduce a frequency of interconnections, a switching operation is additionally required. Consequently, although high-speed access is realized, variations in transistor characteristics based on process subdivision cannot be resolved.
In addition, a precharge operation must be performed for each bit line and global bit line. Consequently, power consumption becomes large if a global bit line is provided for each bit line.